A power MOSFET (metal oxide semiconductor field-effect transistor) is a major carrier conduction type device with its advantages such as high input impedance, fast speed, high frequency, on-resistance with a positive temperature coefficient, wide safety operation area, and usable in parallel. These advantages enable it to be widely used in fields such as industrial control, communication, automobile, computer, portable appliances, home appliances and office appliance. In particular, its application in the switch power supply grows rapidly, thus greatly improving the efficiency in the electronic system.
A long and low doping concentration drift region is required to sustain high breakdown voltage (BV) in a high-voltage device. However, both the long drift region and the low doping concentration will increase the on-resistance (Ron), and thus increase on-state power consumption of the device. There is a relationship of Ron∝BV2.5 between BV and Ron.
The reduction in the specific on-resistance (Ron,sp) of a conventional planar gate VDMOS (vertical double diffusion metal oxide semiconductor) is limited by JFET (junction field-effect transistor) effect as the cell density on a chip increases. A trench MOSFET not only eliminates JFET effect, but also has high channel density, which leads to a low Ron,sp. However, for a high voltage and high current trench MOSFET, the drift region resistance constitutes most part of the total resistance of the device; the problem of silicon limit is thus still not solved.
U.S. Pat. No. 4,754,310 by Coe D. J. from PHILIPS CORP [US], titled High Voltage Semiconductor Device, filed in 1988, proposed for the first time a method of taking the alternate p-column region and n-column region as a voltage-sustaining region in a lateral high-voltage MOSFET (LDMOSFET) to replace the lightly-doped drift region of single conduction type (n type or p type) in the traditional power devices as a voltage-sustaining layer.
In U.S. Pat. No. 521,627, 1993, semiconductor power devices with alternation conductivity type high-voltage breakdown regions, an alternate p-column region and n-column region as a drift layer, called “composite buffer layer”, is used in a longitudinal power device, particularly a longitudinal MOSFET.
In 1997, Tatsuhiko Fujihira (theory of semiconductor superjunction devices, Japanese Journal of Applied Physics, 1997) generalized the above concepts and proposed a “superjunction theory”. Thereafter, the concept of “superjunction (SJ)” is cited and further verified by many device researchers.
As for the voltage-sustaining layer of a superjunction MOSFET, in addition to the depletion along a direction of source-drain region, the p-column region and n-column region therein are mutually depleted, thus the entire voltage-sustaining layer is fully depleted under higher drain voltage, similar to an intrinsic layer, thereby the breakdown voltage of the device may be improved. Meanwhile, a higher concentration may be used in the n-column region in the superjunction, thereby facilitating the reduction of the on-resistance.
The SJ structure is introduced into a power VDMOS to reduce the Ron and maintain a high BV. However, the fabrication process of a high performance superjunction VDMOS is relatively complex and costly. First, the higher the BV of a VDMOS is, the deeper the longitudinal p-column and n-column are. The conventional “superjunction” structure is formed by multiple implantations, multiple epitaxy and annealing. A higher voltage SJ VDMOS are formed by more times the epitaxy and implantations. Therefore, the process becomes more difficult and the cost is higher for a higher breakdown voltage VDMOS. Furthermore, it is very difficult to obtain a high-concentration, narrow-stripe and alternate p- and n-column by using implantations, epitaxy followed by annealing. Second, the electrical properties of the “superjunction” device is very sensitive to charge imbalance, the width and concentration of the p-column region and n-column region must thus be controlled accurately in the process to avoid deterioration of the electrical properties of the device. Third, the reverse recover of the body diode of the device is hardened, and in a high current application, there are problems such as the reduction of the breakdown voltage and the increase of the on-resistance caused by the enlargement of the lateral PN junction depletion layer.
In the document “Shallow Angle Implantation for Extended Trench Gate Power MOSFETs With Super Junction Structure, ISPSD, 2001, Yoshiyuki Hattori, Takashi Suzuki, Masato Kodama, Eiko Hayashii, and Tsutomu Uesugi”, it has shown a trench gate superjunction VDMOS where the SJ has been formed by shallow angle implantation in an epitaxial wafer. The process cost to form SJ structure is reduced to some extent. Due to the characteristics of such a process, the p-column or n-column can be made very narrow, thus the process possesses market prospect well in the low power consumption application field. However, such a process also requires accurate control of the thickness of the oxide layer through which the impurities are implanted, and the breakdown voltage is improved in a limited range.
In his U.S. Pat. No. 7,230,310B2, it has proposed an idea of improving electrical properties by using p- or/and n-column semiconductor region and high-K dielectric region. The structure enlarges the safety operation area, reduces the on-resistance of the device in high current application. In this structure, firstly, the HK dielectric is placed outside the region below the gate; secondly, the gate is a planar gate not a trench gate, and the trench filled with high k dielectric therefore is formed by separately etching; thirdly, the patent has not presented how to manufacture the SJ in the proposed structure, just describe the method for forming p- or n-column with HK dielectric region in a cell. It is very difficult to form a high-concentration, narrow-stripe and alternate p- and n-column if using implantations, epitaxy followed by annealing.